1. Field of the Invention
The present invention relates to a method and an apparatus for statically analyzing variations in source voltage of a semiconductor device such as an LSI without test patterns when designing power source wiring for the semiconductor device.
When designing a power source for an LSI, it is important to reduce the current density in the wiring of the power source and minimize variations in source voltage that are dependent on maximum current consumption. The reason why the voltage variations must be minimized is because they increase delays, decrease operation frequencies, and cause malfunctions. Designing a proper power source for recent LSIs is difficult because the scale, the integration, the operating speed, and the power consumption of the LSIs are increasing.
2. Description of the Related Art
An LSI is an integration of cells that are each made of transistors. When designing an LSI, power source wiring of the LSI is tested cell by cell, or transistor by transistor by decomposing each cell into transistors.
The cell-by-cell test externally applies test patterns to a target LSI, simulates the operation of the LSI, calculates an average current consumption of the LSI, and determines whether or not the power source wiring of the LSI can secure a current density that is suitable for the average current consumption. The topology and width of power source wiring must be determined to satisfy a specified current density. Calculating a maximum power consumption according to the cell-by-cell test requires a long time for measurements and a large quantity of data, and therefore, this test does not consider, in the power source designing stage, variations in source voltage related to the maximum power consumption.
The transistor-by-transistor test externally applies test patterns to a target LSI, simulates the operation of the LSI, and calculates not only a current density in power source wiring of the LSI but also variations in source voltage thereof. This test, however, cannot completely verify an LSI chip because the LSI chip is too large to carry out the test thereon.
The cell-by-cell test externally applies test patterns to a target LSI, simulates the operation of the LSI, and calculates the power consumption thereof. The operation of the LSI in the test is dependent on the test patterns. If the test patterns are faithful to the actual operation of the LSI, the calculated power consumption will be correct.
It is difficult, however, to prepare test patterns that are faithful to the actual operation of a given LSI. Usually, the test patterns produce a partial operation of a given LSI and lead to an incorrect calculation of a power consumption for the LSI.
If the test patterns are proper for simulating the actual operation of the LSI, the average power consumption of the LSI will easily be obtained by integrating current flowing through the LSI for a total operation time of the LSI. Calculating a maximum current consumption of the LSI, however, requires superposing partial current waveforms along a time axis. This superposing process requires considerable computer resources and time, and therefore, it is impossible to use the cell-by-cell test to deal with recent large LSIs due to the processing time and computer resource requirements.
The transistor-by-transistor test may precisely simulate the power consumption of a given LSI, but in practice, it cannot test the whole of a given LSI chip due to the large circuit size thereof.